Circuit-Layout Co-optimization for Extremely Regular Design Fabrics in Nanoscale ICs

The manufacturability benefits of restricted design style have long been recognized in the implementation of SRAM and FPGA circuits. However, the ASIC community has shied away from layout restrictions for the fear of stifling designers’ creativity and creating an inefficient area, and thus cost, product. Nevertheless, as the design features required began to approach nanometer-scale dimensions, the inability to guarantee the process window across the entire design space has led to substantial yield losses and raised questions about existing design assumptions. This dissertation presents a regular fabric based design methodology that embraces a restricted layout style required for enabling successful manufacturing of the sub-32 nm technology nodes. Unlike the vast number of layout geometries allowed by design rules, the regular design fabric forms a new interface between the process and design communities to succinctly communicate the set of permitted layout constructs. While the manufacturability benefits are provided by this new interface, an area efficient implementation of an SoC requires careful co-optimization of allowable layout patterns, process options, and circuit topologies. In this thesis, we present three styles of uni-directional regular design fabrics created by considering trade-offs between design area and process capabilities. Furthermore, we demonstrate that process-driven layout restrictions will force the revision of trusted circuit topologies. In particular, the area efficiency of multiplexers and flip-flops can be improved by migrating from transmission and tri-state based circuit topologies to an AOI-based style. Also, we implemented a framework for the extraction of layout patterns used in the design. By utilizing this framework, we developed layout optimization heuristics and design strategies that can further reduce the set of necessary layout patterns. The use of this methodology would enable correct-by-construction design by allowing for full silicon qualification of the required layout patterns. The future success of the semiconductor industry will depend on its willingness to accept this paradigm shift, which aims to reduce process and design complexity, while at the same time maintaining the cost scaling trends.